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integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 1 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? copyright ? 2003 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. flexbanktm is a trademark of fujitsu limited, japan. embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc 3.0 volt multi-chip package (mcp) ? 128 mbit simultaneous operation flash memory and 32 mbit pseudo static ram preliminary information march 2003 mcp features ? power supply voltage 2.7v to 3.3v high performance: flash: 70ns maximum access time psram: 65ns maximum access time package: 107-ball bga operating temperature: -30c to +85c flash features power dissipation: read current at 1 mhz: 4 ma maximum read current at 5 mhz:18 ma maximum sleep mode: 5 a maximum user configurable banks flash 1 (64 mbit) bank a1: 8mbit (8kb x 8 and 64kb x 15) bank b1: 24mbit (64kb x 48) bank c1: 24mbit (64kb x 48) bank d1: 8mbit (8kb x 8 and 64kb x 15) flash 2 (64 mbit) bank a2: 8mbit (8kb x 8 and 64kb x 15) bank b2: 24mbit (64kb x 48) bank c2: 24mbit (64kb x 48) bank d2: 8mbit (8kb x 8 and 64kb x 15) user chooses two virtual banks from a combination of four physical banks simultaneous r/w operations (dual virtual bank): zero latency between read and write operations; data can be programmed or erased in one bank while data is simultaneously being read from the other bank low-power mode: a period of no activity causes flash to enter a low-power state erase suspend/resume: suspends of erase activity to allow a read in the same bank sector erase architecture: 16 sectors of 4k words each and 126 sectors of 32k words each in word mode. any combination of sectors, or the entire flash can be simultaneously erased erase algorithms: automatically preprograms/erases the flash memory entirely, or by sector program algorithms: automatically writes and verifies data at specified address hidden rom region: 256 byte with a factory-serialized secure electronic serial number (esn), which is accessible through a command sequence data polling and toggle bit: detects the completion of the program or erase cycle ready-busy outputs (ry/ by ) detection of program or erase cycle completion for each flash chip over 100,000 write/erase cycles low supply voltage (vccf 2.5v) inhibits writes wp /acc input pin: if v il , allows partial protection of boot sectors if v ih , allows removal of boot sector protection if vacc, program time is improved psram features (32 mb density) power dissipation: operating: 25 ma maximum standby: 110 a maximum chip selects: ce1 r, ce2r power down feature using ce2r sleep mode: 10 a maximum nap: 65 a maximum 8 mbit partial: 80 a maximum data retention supply voltage: 2.1 v to 3.3v byte data control: lb (dq0?dq7), ub (dq8?dq15)
2 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? general description this 107-ball mcp is a space-saving combination of 3 memories: two 64mbit flash and one 32mbit pseudo sram. each 64mbit flash (flash1 and flash 2) contains 4,194,304 words and the 32mbit psram contains 2,097,152 words. each word is 16 bits wide. data lines dq0-dq15 handle the access for all three memories. write enable, output enable, and a0-a20 are shared among the three memories. single byte data on the psram can be accessed one at a time on dq0-dq7 or dq8-dq15 by using lb or ub , respectively. the package uses a 3.0v power supply for all operations. no other source is required for program and erase operations. the flash can be programmed in system using this 3.0v supply, or can be programmed in a standard eprom programmer. the flash chips are compatible with the jedec flash command set standard. the flash access time is 70ns and the psram access time is 65ns. each flash memory implements an architecture composed of two virtual banks that allows simultaneous operation on each bank. optimized performance can be achieved by first initializing a program or erase function in one bank, then immediately starting a read from the other bank. both operations would then be operating simultaneously on the same chip, with zero latency. mcp block diagram gnd gnd v ccf 2 ry/ by 2 32-mbit psram 32-mbit flash memory dq0-dq15 lb ub we oe ce1 r ce2r a0-a20 v ccr pe (flash 2) a0-a21 ce f 2 reset 2 wp /acc 64-mbit flash memory (flash 1) a0-a21 reset 1 ce f 1 gnd v ccf 1 ry/ by 1 a0-a21
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 3 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? pin descriptions a0-a20 address inputs, common a21 address input, both flash dq0-dq15 data inputs/outputs, common reset 1 reset, flash1 reset 2 reset, flash2 ce1 r, ce2r chip enable, psram ce f1 chip enable, flash1 ce f2 chip enable, flash2 oe output enable, common we write enable, common pe partial enable, psram lb lower-byte control, psram ub upper-byte control, psram wp /acc write protect/acceleration pin, both flash ry/ by1 ready/busy output , flash1 ry/ by2 ready/busy output , flash2 nc no connection du do not use vccf1 power, flash1 vccf2 power, flash2 vccr power, psram gnd ground, common pin configuration (128 mb flash and 32 mb psram) package code: b 107 ball fbga (top view) (9.00 mm x 10.00 mm body, 0.8 mm ball pitch) 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k l m nc nc nc nc nc nc nc a3 a2 a1 a0 ce f1 ce 1r a7 a6 a5 a4 gnd oe dq0 dq8 lb ub a18 a17 dq1 dq9 dq10 dq2 ce f2 wp / acc reset 1 ry/ by 1 dq3 vccf1 dq11 vccf2 nc we ce2r a20 dq4 vccr nc nc a8 a19 a9 a10 dq6 dq13 dq12 dq5 a11 a12 a13 a14 pe dq15 dq7 dq14 a15 a21 nc a16 vccf1 gnd nc nc nc nc nc nc shared flash only psram only nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc du du du du gnd reset 2 ry/ by 2 gnd
4 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? operation (1,2) c c c c c e e e e e f1 c c c c c e e e e e f2 c c c c c e e e e e 1 1 1 1 1 rce2r oe oe oe oe oe w w w w w e e e e e l l l l l b b b b b s u u u u u b b b b b s p p p p p e e e e e a 21 -a 0 dq 7 -dq 0 dq 15 -dq 8 reset1 reset1 reset1 reset1 reset1 reset2 reset2 reset2 reset2 reset2 wp wp wp wp wp /acc (12) full standby h h h h x x x x h x high-z high-z h h x output disable (3) hh l h h hxxhx (10) high-z high-z h h x l h h h h h x x h x high-z high-z h h x h l h h h h x x h x high-z high-z h h x read from flash 1 (4) l h h h l h x x h valid d out d out hh x read from flash 2 (4) h l h h l h x x h valid d out d out hh x write to flash 1 l h h h h l x x h valid d in d in hh x write to flash 2 h l h h h l x x h valid d in d in hh x read from psram (5) hh l h l hl (9) l (9) h valid d out d out hh x write to psram h h l h h l l l h valid d in d in hh x h h l h h l h l h valid high-z d in hh x h h l h h l l h h valid d in high-z h h x flash 1temporary sector group x x x x x x x x x x x x v id xx unprotection (6) flash 2 temporary sector group x x x x x x x x x x x x x v id x unprotection (6) flash 1 hardware reset x x h h x x x x x x high-z high-z l x x flash 2 hardware reset x x h h x x x x x x high-z high-z x l x boot block sector write protection x x x x x x x x x x x x x x l psram power (7) down program h h h h x x x x l valid high-z high-z h h x psram no read h h l h l h h h h valid high-z high-z h h x psram power down (8) xx x l x xxxxx x x x x x legend : l = vil, h = vih, x = vil or vih. see ?dc characteristics? for voltage levels. notes: 1. other operations except for indicated this column are prohibited. 2. do not apply ce f = vil, ce 1r = vil and ce2r = vih all at once. 3. psram output disable condition should not be kept longer than 1ms. 4. we can be vil if oe is vil, oe at vih initiates the write operations. 5. psram lb , ub control at read operation is not supported. 6. it is also used for the extended sector group protections. 7. the psram power down program can be performed one time after compliance of power-up timings and it should not be re- programmed after regular read or write. 8. psram power down mode can be entered from standby state and all dq pins are in high-z state. ipdr current and data retention depends on the selection of power down program. 9. either or both lb and ub must be low for psram read operation. 10. can be either vil or vih but must be valid before read or write. 11. see ? psram power down program key table ? located in the next page. 12. protect ? outer most ? 2x8k bytes ( 4 words ) on both ends of the boot block sectors. device bus operation
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 5 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? absolute maximum ratings (1,5) rating symbol parameter min. max. unit tstg storage temperature ?55 +125 c t a ambient temperature with power applied ?30 +85 c v in ,v out voltage with respect to ground all pins (2) ?0.3 v cc + 0.3 (6) v v cc f 1, v cc f 2 v cc f supply (2) ?0.3 3.5 v v cc rv cc r supply (2) ?0.3 3.5 v v in reset1 , reset2 (3) -0.5 +13.0 v v acc wp /acc (4) ?0.5 +10.5 v notes: 1. voltage is defined on the basis of gnd = 0 v. 2. minimum dc voltage on input or i/o pins is -0.3 v. during voltage transitions, input or i/o pins may undershoot gnd to -1.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc f 1 + 0.3v , v cc f 2 + 0.3v or vccr + 0.3 v. during voltage transitions, input or i/o pins may overshoot to v cc f 1 + 2.0v , v cc f 2 + 2.0 v or vccr + 1.0 v for periods of up to 20 ns. 3. minimum dc input voltage on reset1 or reset2 pin is -0.5 v. during voltage transitions, reset1 or reset2 pin may undershoot gnd to -2.0 v for periods of up to 20 ns. the voltage difference between input and supply voltage (vin-v cc f 1 or v cc f 2 ) does not exceed 9.0 v. the maximum dc input voltage on the reset pin is +13.0 v that may overshoot to +14.0 v for periods of up to 20 ns. 4. minimum dc input voltage on wp /acc pin is -0.5 v. during voltage transitions, wp /acc pin may undershoot gnd to -2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is +10.5 v which may overshoot to +12.0 v for periods of up to 20 ns, when v cc f 1 or v cc f 2 is applied. 5. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 6. this vcc refers to the minimum of v cc f 1, v cc f 2, or vccr . recommended operating conditions rating symbol parameter min. max. unit t a ambient temperature ?30 +85 c v cc f 1, v cc f 2 v cc f supply voltages 2.7 3.3 v v cc rv cc r supply voltages 2.7 3.3 v note: voltage is defined on the basis of gnd = 0 v.
6 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? dc characteristics symbol parameter test conditions min. typ. max. unit i li input leakage v in =gnd to v cc f, v cc r -1.0 ? +1.0 a i lo output leakage v out =gnd to v cc f, v cc r -1.0 ? +1.0 a i lit reset inputs v cc f=v cc f max., ? ? 35 a leakage current reset = 12.5v i cc 1f flash vcc (1) ce f=v il , oe =v ih tcycle = 5mhz ? ? 18 ma active current (read) tcycle = 1mhz ? ? 4 ma i cc 2f flash vcc active (2) ce f=v il ,??35ma current(program/erase) oe =v ih i cc 3f flash vcc active (5) ce f=v il ,??53ma current oe =v ih (read-while-program) i cc 4f flash vcc active (5) ce f=v il ,??53ma current oe =v ih (read-while-erase) i cc 5f flash vcc active ce f=v il ,??40ma current oe =v ih (erase-suspend-program) i acc wp /acc acceleration v cc f = vcc max, ? ? 20 ma program current wp /acc = v acc max i cc 1r psram vcc active v cc r = vccr max, trc / twc = min ? ? 25 ma current ce 1r=v il , ce2r=v ih , v in =v ih or v il , trc / twc = 1 s ? ? 3 ma i out =0 ma i sb 1f flash vcc v cc f = vccf max, ce f= v cc f + 0.3v, ? 1 5 a standby current (7) reset = v cc f + 0.3v , wp /acc = v cc f + 0.3v i sb 2f flash vcc (7) v cc f = vccf max, reset = gnd + 0.3v, ? 1 5 a standby current wp /acc = v cc f + 0.3v ( reset ) i sb 3f flash vcc (3,7) v cc f = vccf max, ce f = gnd + 0.3v, ? 1 5 a current reset = v cc f + 0.3v, (automatic sleep mode) wp /acc = v cc f + 0.3v, v in = v cc f + 0.3v or gnd + 0.3v i sb 1r psram vcc standby (8) v cc r = vccr max, ce1 r v cc r -0.2v, ? ? 110 a current ce2r v cc r -0.2v, v in 0.2 v or v in v cc r -0.2v i pds r psram v cc power v cc r = v cc r max., ? ? 10 a down current ce1 r v cc r - 0.2 v (sleep mode) ce2r 0.2 v, v in cycle time = t rc min i pdn r psram v cc power (8) v cc r = v cc r max., ? ? 65 a down current ce1 r v cc r - 0.2 v (nap mode) ce2r 0.2 v, v in cycle time = t rc min
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 7 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? dc characteristics (continued) symbol parameter test conditions min. typ. max. unit i pd 8 r psram v cc power v cc r = v cc r max., ? ? 80 a down current ce1 r v cc r - 0.2 v (8m partial) (8) ce2r 0.2 v, v in cycle time = t rc min v il input low level -0.3 ? 0.5 v v ih input high level (flash 1 or flash 2 ) v cc f x 0.75 ? v cc f + 0.3 v v ih input high level (psram) v cc r x 0.75 ? v cc r + 0.3 v v id voltage for sector protection 11.5 ? 12.5 v and temp. unprotection( reset ) (4) v acc voltage for wp /acc 8.5 9.0 9.5 v sector protection/unprotection and program acceleration (4) v ol output low level v cc r = v cc r min., v ccs =v ccs min. ? ? 0.4 v (psram) i ol = 1.0 ma v oh output high level v cc r = v cc r min., v ccs =v ccs min. 2.2 ? ? v (psram) i oh = -0.5 ma v ol output low level v cc f = v cc f min., v ccs =v ccs min. ? ? 0.45 v (flash) i ol = 4.0 ma v oh output high level v cc f = v cc f min., v ccs =v ccs min. v cc f - 0.4 ? ? v (flash) i oh = -0.1 ma v lko flash low vccf 2.3 2.4 2.5 v lock-out voltage notes: 1. icc current listed includes both the dc operating current and the frequency dependent component. 2. icc active while embedded algorithm (program or erase) is in progress. 3. automatic sleep mode enables the low power mode when address remains stable for 150 ns. 4. applicable for only vccf applying. 5. embedded algorithm (program or erase) is in progress. (@5 mhz) 6. isb2 r depends on vin cycle time. please refer to ?appendix a?. 7. standby current listed is for each flash chip. 8. standby and power down currents are reduced with vccr < 3.0 v .
8 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? timing diagram for alternating psram to flash 1 or flash 2 ac characteristics - ce ce ce ce ce timing parameter symbol condition min max unit ce f recover time t ccr ?0?ns ce f hold time t chold ?3?ns ce 1r high to we invalid time for t chwx ?10?ns standby entry ce f ce 1r ce2r t ccr t ccr t ccr t ccr t chwx t chold we
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 9 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flexible sector-erase architecture on flash 1 or flash 2 sector sector bank address k-word address bank address k-word address bank a sa0 4 000000h bank b sa36 32 0e8000h bank a sa1 4 001000h bank b sa37 32 0f0000h bank a sa2 4 002000h bank b sa38 32 0f8000h bank a sa3 4 003000h bank b sa39 32 100000h bank a sa4 4 004000h bank b sa40 32 108000h bank a sa5 4 005000h bank b sa41 32 110000h bank a sa6 4 006000h bank b sa42 32 118000h bank a sa7 4 007000h bank b sa43 32 120000h bank a sa8 32 008000h bank b sa44 32 128000h bank a sa9 32 010000h bank b sa45 32 130000h bank a sa10 32 018000h bank b sa46 32 138000h bank a sa11 32 020000h bank b sa47 32 140000h bank a sa12 32 028000h bank b sa48 32 148000h bank a sa13 32 030000h bank b sa49 32 150000h bank a sa14 32 038000h bank b sa50 32 158000h bank a sa15 32 040000h bank b sa51 32 160000h bank a sa16 32 048000h bank b sa52 32 168000h bank a sa17 32 050000h bank b sa53 32 170000h bank a sa18 32 058000h bank b sa54 32 178000h bank a sa19 32 060000h bank b sa55 32 180000h bank a sa20 32 068000h bank b sa56 32 188000h bank a sa21 32 070000h bank b sa57 32 190000h bank a sa22 32 078000h bank b sa58 32 198000h bank b sa23 32 080000h bank b sa59 32 1a0000h bank b sa24 32 088000h bank b sa60 32 1a8000h bank b sa25 32 090000h bank b sa61 32 1b0000h bank b sa26 32 098000h bank b sa62 32 1b8000h bank b sa27 32 0a0000h bank b sa63 32 1c0000h bank b sa28 32 0a8000h bank b sa64 32 1c8000h bank b sa29 32 0b0000h bank b sa65 32 1d0000h bank b sa30 32 0b8000h bank b sa66 32 1d8000h bank b sa31 32 0c0000h bank b sa67 32 1e0000h bank b sa32 32 0c8000h bank b sa68 32 1e8000h bank b sa33 32 0d0000h bank b sa69 32 1f0000h bank b sa34 32 0d8000h bank b sa70 32 1f8000h bank b sa35 32 0e0000h bank c sa71 32 200000h
10 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flexible sector-erase architecture on flash 1 or flash 2 (continued) sector sector bank address k-word address bank address k-word address bank c sa72 32 208000h bank c sa107 32 320000h bank c sa73 32 210000h bank c sa108 32 328000h bank c sa74 32 218000h bank c sa109 32 330000h bank c sa75 32 220000h bank c sa110 32 338000h bank c sa76 32 228000h bank c sa111 32 340000h bank c sa77 32 230000h bank c sa112 32 348000h bank c sa78 32 238000h bank c sa113 32 350000h bank c sa79 32 240000h bank c sa114 32 358000h bank c sa80 32 248000h bank c sa115 32 360000h bank c sa81 32 250000h bank c sa116 32 368000h bank c sa82 32 258000h bank c sa117 32 370000h bank c sa83 32 260000h bank c sa118 32 378000h bank c sa84 32 268000h bank d sa119 32 380000h bank c sa85 32 270000h bank d sa120 32 388000h bank c sa86 32 278000h bank d sa121 32 390000h bank c sa87 32 280000h bank d sa122 32 398000h bank c sa89 32 290000h bank d sa124 32 3a8000h bank c sa90 32 298000h bank d sa125 32 3b0000h bank c sa91 32 2a0000h bank d sa126 32 3b8000h bank c sa92 32 2a8000h bank d sa127 32 3c0000h bank c sa93 32 2b0000h bank d sa128 32 3c8000h bank c sa94 32 2b8000h bank d sa129 32 3d0000h bank c sa95 32 2c0000h bank d sa130 32 3d8000h bank c sa96 32 2c8000h bank d sa131 32 3e0000h bank c sa97 32 2d0000h bank d sa132 32 3e8000h bank c sa98 32 2d8000h bank d sa133 32 3f0000h bank c sa99 32 2e0000h bank d sa134 4 3f8000h bank c sa100 32 2e8000h bank d sa135 4 3f9000h bank c sa101 32 2f0000h bank d sa136 4 3fa000h bank c sa102 32 2f8000h bank d sa137 4 3fb000h bank c sa103 32 300000h bank d sa138 4 3fc000h bank c sa104 32 308000h bank d sa139 4 3fd000h bank c sa105 32 310000h bank d sa140 4 3fe000h bank c sa106 32 318000h bank d sa141 4 3ff000h
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 11 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? user configurable bank architecture table - flash 1 or flash 2 virtual bank 1 virtual bank 2 bank split volume combination volume combination choice 1 8 mbit bank a 56 mbit bank b, c, d choice 2 24 mbit bank b 40 mbit bank a, c, d choice 3 24 mbit bank c 40 mbit bank a, b, d choice 4 8 mbit bank d 56 mbit bank a, b, c example of virtual banks combination table - flash 1 or flash 2 virtual bank 1 virtual bank 2 bank split volume combination sector size volume combination sector size choice 1 8 mbit bank a 8x4 kword 56 mbit bank b, c, d 8x4 kword 15x32 kword 111x32 kword choice 2 16 mbit bank a,d 16x4 kword 48 mbit bank b,c 96x32 kword 30x32 kword choice 3 24 mbit bank b 48x32 kword 40 mbit bank a, c, d 16x4 kword 78x32 kword choice 4 32 mbit bank a,b 8x4 kword 32 mbit bank c,d 8x4 kword 63x32 kword 63x32 kword notes: 1) when multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. for example, if erasing is taking place at both bank a and bank b, neither bank a nor bank b is read out. they would output the sequence flag once they were selected. meanwhile the system would get to read from either bank c or bank d. 2) each word is made-up of 2 bytes: one upper byte and one lower byte. a kword is 2 10 words.
12 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? simultaneous operation table - flash 1 or flash 2 case virtual bank 1 status virtual bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode (1) 5 autoselect mode read mode 6 program mode read mode 7 erase mode (1) read mode note: 1) by writing erase suspend command on the bank address of sector being erased, the erase operation gets suspended so that it enables reading from or programming the remaining sectors. 2) bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. actually, the bank consists of 4 banks , bank a, bank b, bank c, and bank d. bank address (ba) means to specify each of the banks.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 13 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? sector address table - flash 1 or flash 2 bank address sector address address range bank sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 word mode bank a sa0 0000000000 000000h to 000fffh bank a sa1 0000000001 001000h to 001fffh bank a sa2 0000000010 002000h to 002fffh bank a sa3 0000000011 003000h to 003fffh bank a sa4 0000000100 004000h to 004fffh bank a sa5 0000000101 005000h to 005fffh bank a sa6 0000000110 006000h to 006fffh bank a sa7 0000000111 007000h to 007fffh bank a sa8 0000001xxx 008000h to 00ffffh bank a sa9 0000010xxx 010000h to 017fffh bank a sa10 0000011xxx 018000h to 01ffffh bank a sa11 0000100xxx 020000h to 027fffh bank a sa12 0000101xxx 028000h to 02ffffh bank a sa13 0000110xxx 030000h to 037fffh bank a sa14 0000111xxx 038000h to 03ffffh bank a sa15 0001000xxx 040000h to 047fffh bank a sa16 0001001xxx 048000h to 04ffffh bank a sa17 0001010xxx 050000h to 057fffh bank a sa18 0001011xxx 058000h to 05ffffh bank a sa19 0001100xxx 060000h to 067fffh bank a sa20 0001101xxx 068000h to 06ffffh bank a sa21 0001110xxx 070000h to 077fffh bank a sa22 0001111xxx 078000h to 07ffffh bank b sa23 0010000xxx 080000h to 087fffh bank b sa24 0010001xxx 088000h to 08ffffh bank b sa25 0010010xxx 090000h to 097fffh bank b sa26 0010011xxx 098000h to 09ffffh bank b sa27 0010100xxx 0a0000h to 0a7fffh bank b sa28 0010101xxx 0a8000h to 0affffh bank b sa29 0010110xxx 0b0000h to 0b7fffh bank b sa30 0010111xxx 0b8000h to 0bffffh bank b sa31 0011000xxx 0c0000h to 0c7fffh bank b sa32 0011001xxx 0c8000h to 0cffffh
14 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? sector address table - flash 1 or flash 2 (continued) bank address sector address address range bank sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 word mode bank b sa33 0011010xxx 0d0000h to 0d7fffh bank b sa34 0011011xxx 0d8000h to 0dffffh bank b sa35 0011100xxx 0e0000h to 0e7fffh bank b sa36 0011101xxx 0e8000h to 0effffh bank b sa37 0011110xxx 0f0000h to 0f7fffh bank b sa38 0011111xxx 0f8000h to 0fffffh bank b sa39 0100000xxx 100000h to 107fffh bank b sa40 0100001xxx 108000h to 10ffffh bank b sa41 0100010xxx 110000h to 117fffh bank b sa42 0100011xxx 118000h to 11ffffh bank b sa43 0100100xxx 120000h to 127fffh bank b sa44 0100101xxx 128000h to 12ffffh bank b sa45 0100110xxx 130000h to 137fffh bank b sa46 0100111xxx 138000h to 13ffffh bank b sa47 0101000xxx 140000h to 147fffh bank b sa48 0101001xxx 148000h to 14ffffh bank b sa49 0101010xxx 150000h to 157fffh bank b sa50 0101011xxx 158000h to 15ffffh bank b sa51 0101100xxx 160000h to 167fffh bank b sa52 0101101xxx 168000h to 16ffffh bank b sa53 0101110xxx 170000h to 177fffh bank b sa54 0101111xxx 178000h to 17ffffh bank b sa55 0110000xxx 180000h to 187fffh bank b sa56 0110001xxx 188000h to 18ffffh bank b sa57 0110010xxx 190000h to 197fffh bank b sa58 0110011xxx 198000h to 19ffffh bank b sa59 0110100xxx 1a0000h to 1a7fffh bank b sa60 0110101xxx 1a8000h to 1affffh bank b sa61 0110110xxx 1b0000h to 1b7fffh bank b sa62 0110111xxx 1b8000h to 1bffffh bank b sa63 0111000xxx 1c0000h to 1c7fffh bank b sa64 0111001xxx 1c8000h to 1cffffh bank b sa65 0111010xxx 1d0000h to 1d7fffh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 15 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? sector address table - flash 1 or flash 2 (continued) bank address sector address address range bank sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 word mode bank b sa66 0111011xxx 1d8000h to 1dffffh bank b sa67 0111100xxx 1e0000h to 1e7fffh bank b sa68 0111101xxx 1e8000h to 1effffh bank b sa69 0111110xxx 1f0000h to 1f7fffh bank b sa70 0111111xxx 1f8000h to 1fffffh bank c sa71 1000000xxx 200000h to 207fffh bank c sa72 1000001xxx 208000h to 20ffffh bank c sa73 1000010xxx 210000h to 217fffh bank c sa74 1000011xxx 218000h to 21ffffh bank c sa75 1000100xxx 220000h to 227fffh bank c sa76 1000101xxx 228000h to 22ffffh bank c sa77 1000110xxx 230000h to 237fffh bank c sa78 1000111xxx 238000h to 23ffffh bank c sa79 1001000xxx 240000h to 247fffh bank c sa80 1001001xxx 248000h to 24ffffh bank c sa81 1001010xxx 250000h to 257fffh bank c sa82 1001011xxx 258000h to 25ffffh bank c sa83 1001100xxx 260000h to 267fffh bank c sa84 1001101xxx 268000h to 26ffffh bank c sa85 1001110xxx 270000h to 277fffh bank c sa86 1001111xxx 278000h to 27ffffh bank c sa87 1010000xxx 280000h to 287fffh bank c sa88 1010001xxx 288000h to 28ffffh bank c sa89 1010010xxx 290000h to 297fffh bank c sa90 1010011xxx 298000h to 29ffffh bank c sa91 1010100xxx 2a0000h to 2a7fffh bank c sa92 1010101xxx 2a8000h to 2affffh bank c sa93 1010110xxx 2b0000h to 2b7fffh bank c sa94 1010111xxx 2b8000h to 2bffffh bank c sa95 1011000xxx 2c0000h to 2c7fffh bank c sa96 1011001xxx 2c8000h to 2cffffh bank c sa97 1011010xxx 2d0000h to 2d7fffh bank c sa98 1011011xxx 2d8000h to 2dffffh bank c sa99 1011100xxx 2e0000h to 2e7fffh
16 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? sector address table - flash 1 or flash 2 (continued) bank address sector address address range bank sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 word mode bank c sa100 1011101xxx 2e8000h to 2effffh bank c sa101 1011110xxx 2f0000h to 2f7fffh bank c sa102 1011111xxx 2f8000h to 2fffffh bank c sa103 1100000xxx 300000h to 307fffh bank c sa104 1100001xxx 308000h to 30ffffh bank c sa105 1100010xxx 310000h to 317fffh bank c sa106 1100011xxx 318000h to 31ffffh bank c sa107 1100100xxx 320000h to 327fffh bank c sa108 1100101xxx 328000h to 32ffffh bank c sa109 1100110xxx 330000h to 337fffh bank c sa110 1100111xxx 338000h to 33ffffh bank c sa111 1101000xxx 340000h to 347fffh bank c sa112 1101001xxx 348000h to 34ffffh bank c sa113 1101010xxx 350000h to 357fffh bank c sa114 1101011xxx 358000h to 35ffffh bank c sa115 1101100xxx 360000h to 367fffh bank c sa116 1101101xxx 368000h to 36ffffh bank c sa117 1101110xxx 370000h to 377fffh bank c sa118 1101111xxx 378000h to 37ffffh bank d sa119 1110000xxx 380000h to 387fffh bank d sa120 1110001xxx 388000h to 38ffffh bank d sa121 1110010xxx 390000h to 397fffh bank d sa122 1110011xxx 398000h to 39ffffh bank d sa123 1110100xxx 3a0000h to 3a7fffh bank d sa124 1110101xxx 3a8000h to 3affffh bank d sa125 1110110xxx 3b0000h to 3b7fffh bank d sa126 1110111xxx 3b8000h to 3bffffh bank d sa127 1111000xxx 3c0000h to 3c7fffh bank d sa128 1111001xxx 3c8000h to 3cffffh bank d sa129 1111010xxx 3d0000h to 3d7fffh bank d sa130 1111011xxx 3d8000h to 3dffffh bank d sa131 1111100xxx 3e0000h to 3e7fffh bank d sa132 1111101xxx 3e8000h to 3effffh bank d sa133 1111110xxx 3f0000h to 3f7fffh bank d sa134 1111111000 3f8000h to 3f8fffh bank d sa135 1111111001 3f9000h to 3f9fffh bank d sa136 1111111010 3fa000h to 3fafffh bank d sa137 1111111011 3fb000h to 3fbfffh bank d sa138 1111111100 3fc000h to 3fcfffh bank d sa139 1111111101 3fd000h to 3fdfffh bank d sa140 1111111110 3fe000h to 3fefffh bank d sa141 1111111111 3ff000h to 3fffffh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 17 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? sector address group table - flash 1 or flash 2 sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 0 000000000 sa0 sga1 0 000000001 sa1 sga2 0 000000010 sa2 sga3 0 000000011 sa3 sga4 0 000000100 sa4 sga5 0 000000101 sa5 sga6 0 000000110 sa6 sga7 0 000000111 sa7 01 sga8 0 000010xxx sa8 to sa10 11 sga9 0 0001 xxxxx sa11 to sa14 sga10 0 0010 xxxxx sa15 to sa18 sga11 0 0011 xxxxx sa19 to sa22 sga12 0 0100 xxxxx sa23 to sa26 sga13 0 0101 xxxxx sa27 to sa30 sga14 0 0110 xxxxx sa31 to sa34 sga15 0 0111 xxxxx sa35 to sa38 sga16 0 1000 xxxxx sa39 to sa42 sga17 0 1001 xxxxx sa43 to sa46 sga18 0 1010 xxxxx sa47 to sa50 sga19 0 1011 xxxxx sa51 to sa54 sga20 0 1100 xxxxx sa55 to sa58 sga21 0 1101 xxxxx sa59 to sa62 sga22 0 1110 xxxxx sa63 to sa66 sga23 0 1111 xxxxx sa67 to sa70 sga24 1 0000 xxxxx sa71 to sa74 sga25 1 0001 xxxxx sa75 to sa78 sga26 1 0010 xxxxx sa79 to sa82 sga27 1 0011 xxxxx sa83 to sa86 sga28 1 0100 xxxxx sa87 to sa90 sga29 1 0101 xxxxx sa91 to sa94 sga30 1 0110 xxxxx sa95 to sa98 sga31 1 0111 xxxxx sa99 to sa102 sga32 1 1000 xxxxx sa103 to sa106
18 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash memory autoselect codes table - flash 1 or flash 2 type a 21 to a 12 a 6 a 3 a 2 a 1 a 0 code (hex) manufacturer's code ba lllll 04h device code ba l l l l h 227eh extended device ba l h h h l 2202h code (2) ba l h h h h 2201h sector group sector group l l l h l 01h (1) protection address legend: l = vil, h = vih. see ? dc characteristics? for voltage levels. notes: 1. outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. 2. a read cycle at address (ba) 01h outputs device code. when 227eh was output, this indicates that there will require two additional codes, called extended device codes. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh. . sector address group table - flash 1 or flash 2 (continued) sector a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga33 1 1001 xxxxx sa107 to sa110 sga34 1 1010 xxxxx sa111 to sa114 sga35 1 1011 xxxxx sa115 to sa118 sga36 1 1100 xxxxx sa119 to sa122 sga37 1 1101 xxxxx sa123 to sa126 sga38 1 1110 xxxxx sa127 to sa130 00 sga39 1 111101xxx sa131 to sa133 10 sga40 1 111111000 sa134 sga41 1 111111001 sa135 sga42 1 111111010 sa136 sga43 1 111111011 sa137 sga44 1 111111100 sa138 sga45 1 111111101 sa139 sga46 1 111111110 sa140 sga47 1 111111111 sa141
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 19 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash memory command definitions - flash 1 or flash 2 notes: 1. both read/reset commands are functionally equivalent, resetting the device to the read mode. 2. this command is valid during fast mode. 3. this command is valid while reset = v id 4. the valid address is a6 to a0. 5. this command is valid during hi-rom mode. 6. the data ?00h? is also acceptable. command sequence 2 1 3 4 4 bus write cycle req'd first bus second bus third bus fourth bus fifth bus sixth bus cycle write cycle write cycle read/write cycle cycle data read / reset (1) fast program (2) erase resume data data addr. addr. addr. addr. data addr. data addr. data read / reset (1) sga 60h sga ? sga ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 55h ? ? ? ? ? ? ? ? ? ? ? f0h aah b0h ? ra ? ? ? 55h aah f0h ? rd ? ? ? sd ? ? 40h 88h ba xxxh 30h a0h 90h 98h 55h set to fast mode (2) autoselect program program suspend program resume sector erase erase suspend query (4) hi-rom entry 90h pa ? ? 55h aah pd a0h ? ? 3 3 4 1 extended sector group protection (3) reset from fast mode (2) hi-rom exit (5) 555h aah 2aah 55h 555h a0h 00h 1 hi-rom program (5) chip erase 2 3 4 1 1 6 6 1 xxxh 555h 555h 555h ba ba 555h 555h 555h 555h (ba) 55h aah aah 2aah 555h 2aah (ba) 555h 2aah 555h ? ? ? ? ? ? ? ?? ? ? ? ? ? ? 30h ? ? ? ? aah aah 2aah 2aah 55h 55h 555h 555h 80h 80h 555h 555h aah aah 2aah 2aah 55h 55h 55h 555h sa 10h 30h ? ? ?? ? ? ? ? ? ? ba b0h ? ? ?? ? ? ? ? ? ? 60h 555h aah 2aah 55h 555h 20h xxxh pa pd ?? ? ? ? ? ? ? ba xxxh (6) f0h ? ? ?? ? ? ? ? ? ? ? ? ? ? 2aah 2aah 55h 555h 555h (hrba) 90h xxxh pd ?? ? ? ? ? ? ? ? ? (hra) pa
20 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash memory command definitions - flash 1 or flash 2 (continued) spa = sector group address to be protected. set sector group address and (a6, a3, a2, a1, a0) = (0, 0, 0, 1, 0). sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hi-rom area : 000000h to 00007fh hrba = bank address of the hi-rom area (a21 = a20 = a19 = vil) the system should generate the following address patterns : 555h or 2aah to addresses a10 to a0 both read/reset commands are functionally equivalent, resetting the device to the read mode. command combinations not described in flash memory command definitions are illegal. notes: address bits a21 to a11 = x = ?h? or ?l? for all address commands except or program address (pa), sector address (sa), and bank address (ba), and sector group address (spa). bus operations are defined in "device bus operations?. ra = address of the memory location to be read pa = address of the memory location to be programmed. addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a21, a20, a19, a18, a17, a16, a15, a14, a13, and a12 will uniquely select any sector. ba = bank address (a21, a20, a19) rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of the write pulse.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 21 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? jedec standard parameter symbol symbol cond ition min max unit read cycle time t avav t rc 70 ? ns address to output delay t avqv t acc ce f = v il , oe = v il ?70 ns chip enable to output delay t elqv t ce oe = v il ?70 ns output enable to output delay t glqv t oe ?30 ns chip enable to output high-z t ehqz t df ?25 ns output enable to output high-z t ghqz t df ?25 ns output hold time from addresses, t axqx t oh 0? ns ce f or oe , whichever occurs first reset pin low to read mode ? t ready ?20 s flash read only operations characteristics - flash 1 or flash 2 test conditions : output load : 1 ttl gate and 30 pf input rise and fall times : 5 ns input pulse levels : 0.0 v or vccf timing measurement reference level input : vccf/2 output : vccf/2
22 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash read cycle - flash 1 or flash 2 address dq cef 1 oe we address stable output valid high-z high-z t oeh t rc t oe t df t ce t acc t oh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 23 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash hardware reset reset reset reset reset / read operation timing diagram - flash 1 or flash 2 address dq cef 1 reset address stable output valid high-z t rc t acc t rh t ce t rh t rp t oh
24 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash write/erase/program operations - flash 1 or flash 2 jedec standard parameter symbol symbol min typ max unit write cycle time t avav t wc 70 ?? ns address setup time t avwl t as 0 ?? ns address setup time to oe low ? t aso 12 ?? ns during toggle bit polling address hold time t wlax t ah 45 ?? ns address hold time from ce f or ? t aht 0 ?? ns oe high during toggle bit polling data setup time t dvwh t ds 30 ?? ns data hold time t whdx t dh 0 ?? ns output enable hold time read ? t oeh 0 ?? ns output enable hold time ? t oeh 10 ?? ns toggle and data polling ce f high during toggle bit polling ? t ceph 20 ?? ns oe high during toggle bit polling ? t oeph 20 ?? ns read recover time before write ( oe to ce f )t ghwl t ghwl 0 ?? ns read recover time before write ( oe to we )t ghel t ghel 0 ?? ns we setup time ( ce f to we )t wlel t ws 0 ?? ns ce f setup time ( we to ce f )t elwl t cs 0 ?? ns we hold time ( ce f to we )t ehwh t wh 0 ?? ns ce f hold time ( we to ce f )t wheh t ch 0 ?? ns write pulse width t whwl t wp 35 ?? ns ce f pulse width t eleh t cp 35 ?? ns write pulse width high t whwl t wp 25 ?? ns ce f pulse width high t ehel t cph 25 ?? ns word programming operation (1) t whwh 1t whwh 1 ? 6 100 s sector erase operation (1) t whwh 2t whwh 2 ? 0.5 2.0 s v cc setup time ? t vcs 50 ?? s rise time to v id (2) ? t vidr 500 ?? ns rise time to v acc (3) ? t vaccr 500 ?? ns voltage transition time (2) ? t vlht 4 ?? s write pulse width (2) ? t wpp 100 ?? s
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 25 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash write/erase/program operations - flash 1 or flash 2 (continued) jedec standard parameter symbol symbol min typ max unit oe setup time to we active (2) ? t oesp 4 ?? s ce f setup time to we active (2) ? t csp 4 ?? s recover time from ry/ by ? t rb 0 ?? ns reset pulse width ? t rp 500 ?? ns reset high level period before read ? t rh 200 ?? ns program/erase valid to ry/ by delay ? t busy ?? 90 ns delay time from embedded output enable ? t eoe ?? 70 ns erase time-out time ? t tow 50 ?? s erase suspend transition time ? t spd ?? 20 s notes: 1. does not include preprogramming time. 2. for sector group protection operation. 3. for accelerated program operation.
26 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash write cycle - flash 1 or flash 2 ( we control) notes: 1 . pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. address dq cef oe we a0h dq 7 dout pa 555h pa data polling pd dout t as 3rd bus cycle t ah t wc t rc t oe t ce t oh t df t ds t dh t whwh1 t cs t ch t ghwl t wp t wph
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 27 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash write cycle - flash 1 or flash 2 ( cef control) notes: 1 . pa is address of the memory location to be programmed. 2. pd is data to be programmed at byte address. 3. dq 7 is the output of the complement of the data written to the device. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles out of four bus cycle sequence. address dq cef 1 oe we a0h dq 7 dout pa 555h pa data polling pd t as 3rd bus cycle t ah t wc t ds t dh t whwh1 t ws t wh t ghel t cp t cph
28 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash ac waveforms chip/sector erase operations - flash 1 or flash 2 notes: 1 . sa is the sector address for sector erase. address = 555h for chip erase. address dq cef 1 oe we 55h 10h/ 30h vccf 55h aah 80h aah 555h 2aah 555h 555h 2aah sa * 30h for sector erase t wc t as t ah t cs t ch t wp t wph t vcs t ghwl t ds t dh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 29 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash ac waveforms for data data data data data polling during embedded algorithm operations - flash 1 or flash 2 notes: 1 . dq 7 = valid data (the device has completed the embedded operation.) data in dq 0 /dq 6 cef 1 oe we ry/ by dq data in dq 7 dq0 to dq6 = output flag dq0 to dq6 valid data dq7 = valid data t df t busy t whwh1 or 2 t oe t eoe t oeh t cef1 t ch high - z high - z (1)
30 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash ac waveforms for toggle bit during embedded algorithm operations - flash 1 or flash 2 notes: 1 . dq6 stops toggling (the device has completed the embedded operation). toggle toggle toggle stop outpu t data data data toggle valid data address dq 6 /dq 2 cef 1 oe we t dh t busy t oeh t oe ry/ by t cef t oeh t oeph t ceph t aht t aso t aht t as (1)
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 31 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash back-to-back read/write timing diagram - flash 1 or flash 2 note: 1. this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1: address of virtual bank 1. ba2: address of virtual bank 2. address dq cef 1 oe we ba1 ba1 ba1 t rc t as t ah t acc t ce ba2 (555h) ba2 (pa) ba2 (pa) read command read command read read valid valid valid valid valid output input output input output status t wc t rc t wc t rc t rc t ds t dh t df t df t oeh ( pd ) t ghwl t wp ( a0h ) t oe t ceph t aht t as
32 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash ry/ by by by by by timing diagram during write/erase operations - flash 1 or flash 2 flash reset, reset, reset, reset, reset, ry/ by by by by by timing diagram - flash 1 or flash 2 we c e f ry/ by the rising edge of the last write pulse entire programming or erase operations t busy we reset ry/ by t ready t rp t rb
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 33 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash temporary sector group unprotection - flash 1 or flash 2 reset vccf vid 3v cef 1 we ry /by program or erase command sequence unprotection period t vidr t vcs t vlht t vlht t vlht
34 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash accelerated program - flash 1 or flash 2 wp/ acc vccf vacc vih cef 1 we ry /by acceleration period t vaccr t vcs t vlht t vlht t vlht program command sequence
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 35 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash extended sector group protection- flash 1 or flash 2 notes: 1 . spax : sector group address to be protected, spay : next group sector address to be protected, time-out: time-out window = 250 s (min) reset address a6, a3 a2, a0 a1 cef 1 oe we data vccf 60h 60h 40h 01h 60h spax spay spax time-out t vcs t vidr t vlht t wc t wp t oe t wc
36 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? flash erase and programming performance - flash 1 or flash 2 parameter min. typ. (1) max. unit remarks sector erase time ? 0.5 2.0 s excludes programming time prior to erasure word programming time ? 6.0 100 s excludes system-level overhead chip programming time ? ? 200 s excludes system-level overhead erase/program cycle 100,000 ? ? cycle note: 1. typical erase conditions ta = 25c, vccf_1 & vccf_2 = 2.9v. typical program conditions ta = 25c, vccf_1 & vccf_2 = 2.9v. data= checker
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 37 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? mode data retention area a16 a17 a18 a19 a20 mode select area select x l h x l h h h l l l h x l h x x l h x none bottom 8m only top 8m only none nap 8m partial sleep a16 l l h h a17 l h h h mode nap reserved 8m partial sleep area bottom reserved reserved top a18 l l h h a19 l h l h a20 l x x h definition a16 a17 a20 a18 a19 key mode select area select basic key table available key table (3) (2) (4) (4,5) psram power down program key table notes: 1: the power down program can be performed one time after compliance of power-up timings and it should not be re-programmed after regular read or write. unspecified addresses, a0 to a15, can be either high or low during the programming. the reserved key should not be used. 2: top area is from the lowest address location. (i.e., a[20:0] = h)) 3: bottom area is from the highest address location. (i.e., a[20:0] = l) 4: nap and sleep do not retain the data and area select is ignored. 5: default state. power down program to this sleep mode can be omitted.
38 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram read operations parameter symbol min max. unit read cycle time t rc 70 ? ns chip enable access time (1,3) t ce ? 65 ns output enable access time (1) t oe ? 40 ns address access time (1,4) t aa ? 65 ns output data hold time (1) t oh 5 ? ns ce 1r low to output low-z (2) t clz 5 ? ns oe low to output low-z (2) t olz 0 ? ns ce 1r high to output high-z (2) t chz ? 20 ns oe high to output high-z (2) t ohz ? 20 ns address setup time to ce 1r low (5) t asc -5 ? ns address setup time to oe (3,6) t aso 25 ? ns address setup time to oe (7) t aso ( abs )10 ? ns lb/ub set up time to ce 1r low (5) t bsc -5 ? ns lb/ub set up time to oe low t bso -10 ? ns address invalid time (4) t ax ? 5 ns address hold time from ce 1r low (4) t clah 70 ? ns address hold time from oe low (4,8) t olah 45 ? ns address hold time from ce 1r high t chah -5 ? ns address hold time from oe high t ohah -5 ? ns lb/ub hold time to ce 1r low t chbh -5 ? ns lb/ub hold time to oe low t ohbh -5 ? ns ce 1r low to oe low delay time (3,6,8,9) t clol 25 1000 ns oe low to ce 1r high delay time (8) t olch 45 ? ns ce 1r high pulse width t cp 12 ? ns oe high pulse width (6,8,9) t op 25 1000 ns oe high pulse width (7) t op ( abs )12 ? ns notes: 1. the output load is 30 pf. 2. the output load is 5 pf. 3. the t ce is applicable if oe is brought to low before ce 1r goes low and is also applicable if actual value of both or either t aso or t clol is shorter than specified value. 4. applicable only to a0 and a1 when both ce 1r and oe are kept at low for the address access. 5. applicable if oe is brought to low before ce 1r goes low. 6. the t aso , t clol (min) and t op (min) are reference values when the access time is determined by t oe . if the actual value of each parameter is shorter than the specified minimum value, t oe becomes longer by the amount of subtracting actual value from specified minimum value. for example, if actual t aso , t aso (actual) , is shorter than specified minimum value, t aso (min) , during oe control access (i.e., ce 1r stays low) , the t oe becomes t oe (max) + t aso (min) - t aso (actual) . 7. the t aso [ abs ] and t op [ abs ] are the absolute minimum values during oe control access. 8. if actual value of either t clol or t op is shorter than specified minimum value, both t olah and t olch become t rc (min) - t clol (actual) or t rc (min) - t op (actual) . 9. maximum value is applicable if ce 1r is kept at low .
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 39 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram write operations value parameter symbol min. max. unit write cycle time (1) t wc 70 ? ns address setup time (2) t as 0? ns address hold time (2) t ah 35 ? ns ce 1r write setup time t cs 0 1000 ns ce 1r write hold time t ch 0 1000 ns we setup time t ws 0? ns we hold time t wh 0? ns lb adnd ub setup time t bs -5 ? ns lb adnd ub hold time t bh -5 ? ns oe setup time (3) t oes 0 1000 ns oe hold time (3,4) t oeh 25 1000 ns oe hold time (5) t oeh ( abs )12?ns oe high to ce 1r low setup time (6) t ohcl -5 ? ns oe high to address hold time (7) t ohah -5 ? ns ce 1r write pulse width (1,8) t cw 45 ? ns we write pulse width (1,8) t wp 45 ? ns ce 1r write recovery time (1,9) t wrc 10 ? ns we write recovery time (1,3,9) t wr 10 1000 ns data setup time t ds 15 ? ns data hold time t dh 0? ns ce 1r high pulse width (9) t cp 12 ? ns notes: 1. minimum value must be equal or greater than the sum of actual t cw (or t wp ) and t wrc (or t wr ). 2. new write address is valid from either ce 1r or we that is brought to high. 3. maximum value is applicable if ce 1r is kept at low and both we and oe are kept at high. 4. the t oeh is specified from end of t wc (min), and is a reference value when access time is determined by t oe . if actual value is shorter than specified minimum value, toe becomes longer by the amount of subtracting actual value from specified minimum value. 5. the t oeh [ abs ] is the absolute minimum value if write cycle is terminated by we and ce 1r stay low. 6. t ohcl (min) must be satisfied if read operation is not performed prior to write operation. in case oe is disabled after t ohcl (min), we low must be asserted after t rc (min) from ce 1r low. in other words, read operation is initiated if t ohcl (min) is not satisfied. 7. applicable if ce 1r stays low after read operation. 8. t cw and t wp are applicable if write operation is initiated by ce 1r and we , respectively. 9. t wrc and t wr are applicable if write operation is terminated by ce 1r and we , respectively. the t wr (min) can be ignored if ce 1r is brought to high together or after we is brought to high. in such a case, the t cp (min) must be satisfied.
40 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram power down parameters value parameter symbol min. max. unit ce2r low setup time for power down entry t csp 10 ? ns ce2r low hold time after power down entry t c 2 lp 70 ? ns ce 1r high hold time following ce2r high after power down exit sleep mode only t chh 350 ? s ce 1r high setup time following ce2r high after power down exit t chhn 1 ? s (except for sleep mode) ce 1r high setup time following ce2r high after power down exit t chs 10 ? ns ce 1r high to pe low setup time (1) t eps 70 ? ns pe power down program pulse width (1) t ep 70 ? ns pe high to ce 1r low hold time (1) t eph 70 ? ns address setup time to pe high (1) t eas 15 ? ns address setup time from pe high (1) t eah 0 ? ns psram other timing parameters value parameter symbol min. max. unit ce 1r high to oe invalid for standby entry t chox 10 ? ns ce 1r high to we invalid for standby entry (1) t chwx 10 ? ns ce2r low hold time after power-up (2) t c 2 lh 50 ? s ce2r high hold time after power-up (3) t c 2 hl 50 ? s ce 1r high hold time following ce2r high after power-up (2) t chh 350 ? s input transition time (4) t t 125 ns notes: 1. unintended data may be written into any address location if t chwx is not satisfied. 2. must satisfy t chh (min) after t c2lh (min) . 3. requires power down mode entry and exit after t c2hl . 4. input transition time (t t ) at ac testing is 5 ns as shown below. if actual t t is longer than 5 ns, it may violate some timing parameters. psram ac test conditions parameter symbol cond ition value unit input high level v ih v cc r = 2.7v to 3.3v 2.3 v input low level v il v cc r = 2.7v to 3.3v 0.4 v input timing measurement level v ref v cc r = 2.7v to 3.3v 1.3 v input transition time t t between v il and v ih 5ns note: 1. applies to power down program.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 41 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram read timing ( oe control access) psram read timing ( ce 1r control access) note: ce2r, pe and we must be high during read cycle. either or both lb and ub must be low when both ce 1r and o e are low. address valid data output dq (output) address valid t rc t rc t ohah t ohah t ohz t olz t oh t olz t ce t aso address valid t aso lb / ub t bso t ohz valid data output ce 1r oe t oe t op t oh t ohbh t bso t ohbh t clol t oe t olch address valid data output oe ce 1r dq (output) address valid t rc t rc t chah t ce t chah t chz t clz t oh t clz t ce t asc address valid t cp t asc lb / ub t bsc t chz valid data output t oh t chbh t bsc t chbh note: ce2r, pe and we must be high during read cycle. either or both lb and ub must be low when both ce 1r and o e are low.
42 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram read timing (address access after oe control access) psram read timing (address access after ce 1r control access) address (a2-a0) valid data output dq (output) address valid t ohah t olah t oh t olz address valid t ax lb / ub t bso valid data output ce 1r oe t oh t ohbh t oe t ohz address (a20-a3) address valid t rc t rc address valid t aso t aa (no change) address (a2-a0) address valid t chah t clah address valid address (a20-a3) address valid t rc t rc address valid t asc t aa t ax oe valid data output dq (output) t oh t clz valid data output t oh ce 1r (no change) t ce t chz t bsc t chbh ub, lb note: ce2r, pe and we must be high during read cycle. either or both lb and ub must be low when both ce 1r and o e are low. note: ce2r, pe and we must be high during read cycle. either or both lb and ub must be low when both ce 1r and o e are low.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 43 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram write timing ( ce 1r control) psram write timing ( we control, single write operation) note: ce2r and pe must be high during write cycle. address valid data input ce 1r oe dq (input) address valid we ub, lb t ds t dh t as t as t ah t wc t bs t ohcl t cw t wrc t wh t ws t bh t bs t ws address ce 1r dq (input) oe valid data in p ut address valid we ub, lb t ohah t as t bs t oes t ohbh t ohcl t cs t wp t wr t bh t cp t dh t ds t ohz t ah t wc t ch t as note: ce2r and pe must be high during write cycle.
44 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram write timing ( we control, continuous write operation) psram read / write timing ( ce 1r control) note: write address is valid from either ce 1r or we of last falling edge. note: ce2r and pe must be high during write cycle. address ce 1r dq (input) oe valid data input address valid we ub, lb t ohah t as t wc t as t ah t ohcl t cs t bs t oes t ohz t ds t dh t bs t bh t wp t wr t bh address ce 1r dq oe valid data input write address t dh t asc we ub, lb t as read address t olz read data output t cp t wh t ws t bs t ohcl t chz t oh t ds t bh t wh t ws t clol t wrc t wc t ah t cw t bso t chah t chbh
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 45 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? address ce 1r dq oe write data in p ut t oeh write address we ub, lb read address read data output t chah t bsc t rc t as t wrc t wrc (min) t asc t wh t ws t bh t dh t clz t ce t oh t chz t ohcl t bs t chbh t ws t wh t cp psram read / write timing ( ce 1r control) psram read / write timing (read = oe control, write = we control) note: the t oeh is specified from the time satisfied oth t wrc and t wr (min). note: ce 1r can be tied to low for we and oe controlled operation. when ce 1r is tied to low, output is exclusively controlled by oe . address ce 1r dq oe write data input write address t dh t aso we ub, lb t ohah t as read address t olz t oh read data output low t wc t ah t wp t wr t bh t oeh t ds t ohz t oes t bs t ohbh t bso
46 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram read / write timing (read = oe control, write = we control) note: ce 1r can be tied to low for we and oe controlled operation. when ce 1r is tied to low, output is exclusively controlled o e . address ce 1r dq oe write data input t oeh write address t aso we ub, lb read address t dh read data output t bh t ohah t bs low t ohbh t rc t as t wr t bso t oe t olz t oh t ohz t oes
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 47 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram power down timing psram standby entry and exit timing note: this power down mode can be also used for power-up timing #2 except that t chhn can not be used at power-up timing. ce 1r address a20-a16 t eps pe t ep t eah key t eas t eph note: ce2r must be high for power down programming. any other inputs not specified above can be either high or low. ce 1r dq t chh (chhn) t chs t c2lp t csp ce2r high - z power down entry power down mode power down exit
48 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram power up timing 2 psram power up timing 1 ce 1r v cc r tc2lh ce2r tchs tchh 0v vccr min ce 1r vccr tc2hl ce2r tchs tchh 0 v vccr min tc2lp tcsp tc2hl note: the t c2hl specifies from ce2r low to high transition after vccr reaches specified minimum level. ce 1r must be brought to high prior to or together with ce2r low to high transition. note: the t c2lh specifies after vccr reaches specfied minimum level.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 49 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? psram data retention switching characteristics symbol parameter conditions min. max. unit v dr vccr data retention supply voltage ce1 r = ce2r v cc r -0.2v or , 2.1 3.3 v ce1 r = ce2r = v ih i dr vccr data retention supply current 2.1 v v cc r 2.7 v, ? 1.5 ma v in = v ih (1) or v il ce1 r = ce2r = v ih (1) , i out = 0 m a i dr 1 vccr data retention supply current 2.1 v v cc r 2.7 v, ? 100 a v in 0.2 v or v in v cc r -0.2 v, ce1 r = ce2r v cc r -0.2 v i out = 0 ma t drs data retention setuptime 2.7 v v cc r 3.3 v, 0? ns at data retention entry t drr data retention recoverytime 2.7 v v cc r 3.3 v, 200 ? ns after data retention ? v/ ? t v ccr voltage transition time ? 0.2 ? v/s note: 1. 2.0 v v in v cc r + 0.3 psram data retention timing note: 1. 2.0 v v ih v cc r + 0.3 v 3.3v 2.7v 2.1v 0.4v gnd t drs t drr vccr ce2r ce 1r ce 1r = ce2r >vccr - 0.2v or v ih (1) min data retention mode data bus must be in high-z at data retention entry ? v/ ? t ? v/ ? t
50 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? pin capacitance symbol parameter conditions min. max. unit c in input capacitance v in = 0 v -20pf c out output capacitance v out = 0 v -25pf c in 2 control pin capacitance v in = 0 v -25pf notes: 1. test conditions t a = +25 c , f = 1.0 mhz handling of package: please handle this package carefully because the sides of the package have acute angles. caution: 1) the high voltage (vid) cannot be applied to address pins and control pins except reset. exception is when autoselect and sector group protection function are used. then the high voltage (vid) can be applied to reset. 2) without the high voltage (vid) sector group protection can be achieved by using the ?extended sector group protection? command.
integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 51 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? 10 9 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 9 10 a b c d e f g h j k l m a b c d e f g h j k l m ? 0.40 + 0.10/?0.05 (107x) d e e a1 seating plane a d1 e1 e symbol min. typ. max. units a 1.15 1.25 1.40 mm a1 0.05 0.10 0.15 mm d 9.90 10.00 10.10 mm d1 ? 8.80 ? mm e 8.90 9.00 9.10 mm e1 ? 7.20 ? mm e ? 0.80 ? mm mini ball grid array ? 107-ball bga package code: b ( 9.00 mm x 10.00 mm body, 0.8 mm ball pitch )
52 integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 preliminary information rev. 00d 03/24/03 is75v16f128gs32 issi ? ordering information industrial range: -30 o c to +85 o c flash bank flash psram order part no. organization speed(ns) speed(ns) package IS75V16F128GS32-7065BI user configurable 70 65 107-ball bga

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